Organization of an array of memory cells is one of the keys to the density and electrical characteristic of the memory array. Organizational considerations are particularly acute in the area of dynamic Random Access Memories (dRAMSs). DRAMS are generally comprised of memory cells which includes a storage capacitor and a pass transistor controlling flow of charge into and out of one plate of the storage capacitor. Because of the simple structure of the memory cells, high density of the memory array can be achieved. Memory cells are generally arrayed in an X Y grid with the gates of the pass transistors connected along the X-axis (commonly called the row direction), and the sources of the pass transistors connected to bitlines in the Y direction (commonly called the column direction). In lower density memory arrays, the sense amplifier, which receives the data output from the column lines, received the cell signal on a single lead with the sense amplifier comparing the signal on that lead to a reference potential. As memory arrays grew denser and denser, the size of the capacitor in the memory cells grew smaller. Therefore, the signal provided when the capacitor was accessed also grew smaller. As the signal received grew smaller the ambient noise received on the line began to overwhelm the signal received from the capacitor. Therefore, more sophisticated sense amplification techniques were developed. An example of a memory layout and sense amplification technique can be found in Harland, U.S. Pat. No. 4,045,783, issued Aug. 30, 1977 which is hereby incorporated by reference. The technique shown in Harland provides a balanced input to the sense amplifier. Noise signals caused by electrical fields are generated on both of the complementary bitlines. The sense amplifier compares the signal provided on the memory cell bitline verses the signal provided on the balancing bitline. Thus, noise generated on both bitlines (common mode noise) is canceled. However, because balanced bitlines must run parallel to each other, only one memory cell on one of the parallel bitlines may be addressed. When memory cells were larger, the extra space consumed by the pair of bitlines was used by interleaved memory cells. Thus this space disadvantage was not a problem. Modern dRAM memory cell techniques have advanced to the point to where the surface area consumed by a memory cell is nearly as small as the surface area consumed by the bitline running to the memory cell. An example of such a memory cell is found in U.S. Pat. No. 4,797,373, filed Nov. 12, 1987 and assigned to the assignee of this application which is hereby incorporated by reference. With a cell occupying a minimum surface area, the area where a word line passes through a portion of a balanced pair of bitlines where it can not be connected is a memory cell to simply wasted space.
One solution to this problem is an open bitline technique. In this technique one of a pair of balanced bitlines extends from side of the sense amplifier while the other balanced bitline extends from the other side of the sense amplifier. The bitlines on opposite sides of the sense amplifier are interleaved with bitlines from sense amplifiers on the opposite sides of their respective arrays, thereby allowing addressing a memory cell at each crossing of a word line and bitline. This provides a "cross-point array". However, because the bitlines do not run near each other electrically (i.e. parallel); noise generated on one bitline will not be present on the complementary bitline. Thus the signal to noise ratio of the signal stored on the memory cell verses the noise present on the bitlines is much higher than that with the folded bitline concept.